The present invention is generally related to capacitor structures, and more particularly to an improved high field capacitor structure employing a carrier trapping region and having particular application to semiconductor capacitor structures.
Asperities or defects in the silicon surface are generally thought to increase insulator leakage current and lead to low voltage breakdowns in metal-oxide-semiconductor (MOS) devices. This has been dramatically shown for thermal oxides grown on top of polycrystalline silicon by D. J. DiMaria and D. R. Kerr in "Interface Effects and High Conductivity and Oxides Grown From Polycrystalline Silicon", Applied Physics Letters, Volume 27, No. 9, Nov. 1, 1975, pp. 505-507. Thermal oxides grown on top of polycrystalline silicon are important for various types of devices based on Si technology, such as the Floating Avalanche Injection MOS (FAMOS), Rewritable Avalanche Injection Device (RADI), and Charge Coupled Device (CCD). It is believed that these asperities cause locally high fields to occur which in turn lead to localized high dark current densities (via interface limited, Fowler-Nordhiem tunneling) and low voltage breakdown.
Asperities on the surface of metallic substrates of thin film capacitors are believed to cause low field breakdowns in substantially the same manner as that observed in the case of thermal oxides grown on top of polycrystalline silicon. What is required is a way to reduce the high field points or their effect due to asperities between the substrate and the insulator in a capacitor structure in order to improve the leakage current and breakdown voltage of that structure.